搜索资源列表
FT245
- 在FPGA实现一个与外围USB FIFO 通信的FIFO控制核-The FPGA to implement a communication with the external USB FIFO FIFO control nuclear
EP-FIFO-Architecture-of-EZ-USB
- Endpoint FIFO Architecture of EZ-USB FX1 FX2
CYDOWN
- USB FIFO 测试，为测试USB数据传输的性能-USB FIFO test for the performance of the USB transmit
Bulkloop
- USB FIFO 测试，测试USB的传输性能-USB FIFO test for performance of the USB’s transmission
FX2-Slave-FIFO
- usb芯片CY7C68013A例程,接口类型被动先进先出-passive first-in, first-out the usb chip CY7C68013A routine, interface type FIFO
D2XXPG21
- FTDI’s “D2XX Direct Drivers” for Windows offer an alternative solution to our VCP drivers which allows application software to interface with FT232 USB UART and FT245 USB FIFO devices using a DLL instead of a Virtual Com Port. The architecture of the
slave-fifo
- 本程序主要用于开发usb数据传输时的CY7C68013A固件程序，采取的是从模式的数据传输，只要把程序直接下载到EZ-USB中，然后再去写设备端程序就可以了。-This procedure is mainly used for the the CY7C68013A firmware development usb data transmission, taken from the mode of data transmission, and, as long as the program is
cpld-usb
- usb-fpga通讯，从cpld到usb协议芯片slave fifo的通讯过程指导。-The usb-FPGA communication from the CPLD to usb protocol chip slave FIFO communication process guidance.
YJ_EP4
- 与Cpress CY8013所对应的 FPGA端的开发 使用NIOSII NIOSII 连续往USB FIFO 端点里灌数据 上位机不断的接收 陪和我的上位程序可以达到30Mbyte/s 需要上位机程序的去搜索TestUSBSpeedMFCNovember -upload-And Cpress CY8013 corresponding end FPGA development using NIOSII NIOSII continuous irrigation to USB FIFO
fifo
- Renesas USB driver for Linux.
gpif_to_extfifo-fifo-rw
- USB GPIF 接口编程源码，经过验证-The source code for USB GPIF. It was verifed.
fifo
- Renesas USB driver for Linux v2.13.6.
USB-Drive
- 基于CY7C68013A的USB固件配置,可用于实际工程设计.采用的是外接FIFO设计.-USB firmware configuration based on CY7C68013A,Can be used for practical engineering design. The use of external FIFO design.
USB
- USB芯片 的驱动程序，实现FT22332H的异步FIFO模式的数据传输。-USB chip drivers, data transmission FT22332H asynchronous FIFO mode.
fifo
- 使用外部fifo，CY7C68013A USB芯片-readme.txt for FX2_to_extsyncFIFO GPIF FIFO Transactions Auto mode see GPIF Primer section on design examples for operating instructions and details
FX2LP_QFN_AD9245_B1
- CYPRESS FX2 USB 2.0 High speed chip usb fifo with ad9245 40msps adc.
CCD_Array
- Interface TCD1209DG with Altera FPGA and transfer image data to PC via USB using USB FX2 Slave FIFO mode, Only FPGA code included.
fifo_FPGA
- 68013 FIFO 接口程序，USB开发、VHDL开发(68013 FIFO USB VHDL FPGA)
uart_test
- 收发端都采用2M波特率发送串口数据，通过PIN口直接输入输出串口数据，目的是为了跟外围高速器件完成高速的串口数据的收发，普通USB转串口的都只能支持不到1M的波特率，内部采用乒乓FIFO进行时钟域切换以及缓存(The transmitter and receiver are used 2M baud rate serial data transmission, directly through the PIN port serial input and output data, the purp
13_usb_test
- READ 16BIT DATA FROM EP2 FIFO AND SEND TO EP6 FIFO